という指示がちょくちょくあったのでメモ．
intel manual Vol. 3 capter 18 p59-60 より，
[Table 18-11. Core Specificity Encoding]
Bit 15:14
11B All cores
10B Reserved
01B This core
00B Reserved
Some microarchitectural conditions allow detection specificity only at the boundary of physical processors. Some bus events belong to this category, providing specificity between the originating physical processor (a bus agent) versus other agents on the bus. Sub-field encoding for agent specificity is shown in Table 18-12.
[Table 18-12. Agent Specificity Encoding]
Bit 13
0 This agent
1 Include all agents
Some microarchitectural conditions are detectable only from the originating core. In such cases, unit mask does not support core-specificity or agent-specificity encodings. These are referred to as core-only conditions. Some microarchitectural conditions allow detection specificity that includes or excludes the action of hardware prefetches. A two-bit encoding may be supported to qualify hardware prefetch actions. Typically, this applies only to some L2 or bus events. The sub-field encoding for hardware prefetch qualification is shown in Table 18-13.
[Table 18-13. HW Prefetch Qualification Encoding]
Bit 13:12
11B All inclusive
10B Reserved
01B Hardware prefetch only
00B Exclude hardware prefetch
[Table 18-14. MESI Qualification Definitions]
Bit Position 11:8
Bit 11 Counts modified state
Bit 10 Counts exclusive state
Bit 9 Counts shared state
Bit 8 Counts Invalid state
// よく使いそうな16進マスク
//--------------------------------------------------
[Table 18-11. Core Specificity Encoding]
0xc000: All cores
0x4000: This core
[Table 18-12. Agent Specificity Encoding]
0x0000 This agent
0x2000 Include all agents
[Table 18-13. HW Prefetch Qualification Encoding]
0x3000: All inclusive
0x1000: Hardware prefetch only
[Table 18-14. MESI Qualification Definitions]
0x0f00: 全部
// Reference
Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: APPENDIX A
PERFORMANCE-MONITORING EVENTS
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